AT17C010 查看數據表（PDF） - Atmel Corporation

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AT17C010

FPGA Configuration EEPROM Memory 512K and 1M

Atmel Corporation 

AT17C512/010/LV512/010

Pin Configurations (Continued)

8

PDIP/

LAP

Pin

20

PLCC

Pin

Name

I/O

Description

6

14

CEO

A2

O

Chip Enable Output. This signal is asserted Low on the clock cycle following the last

bit read from the memory. It will stay Low as long as CE and OE are both Low. It will

then follow CE until OE goes High. Thereafter, CEO will stay High until the entire

EEPROM is read again.

I

Device selection input, A2. This is used to enable (or select) the device during

programming (i.e., when SER_EN is Low; see the “Programming Specification”

application note for more details).

15

READY

O

Open collector reset state indicator. Driven Low during power-up reset, released

when power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if used). The

DIP/SOIC package.

7

17

SER_EN

I

Serial enable must be held High during FPGA loading operations. Bringing SER_EN

Low enables the 2-wire Serial Programming Mode.

8

20

VCC

+3.3V/+5V power supply pin.

5

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