EVAL-AD7859CB 查看數據表（PDF） - Analog Devices
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EVAL-AD7859CB Datasheet PDF : 29 Pages
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AD7859/AD7859L
TIMING SPECIFICATIONS1 (AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7859 and 1.8 MHz for AD7859L;
TA = TMIN to TMAX, unless otherwise noted)
Parameter 5 V
Limit at TMIN, TMAX
(A, B Versions)
3V
Units
Description
fCLKIN2
t13
t2
tCONVERT
t3
t4
t5
t6
t7
t84
t95
t10
t11
t12
t13
t14
t15
t16
t17
t184
t19
tCAL6
tCAL16
tCAL26
500
4
1.8
100
50
4.5
10
15
5
0
0
55
50
5
40
60
0
5
0
0
55
10
5
1/2 tCLKIN
2.5 tCLKIN
31.25
27.78
3.47
500
4
1.8
100
90
4.5
10
15
5
0
0
55
50
5
40
70
0
5
0
0
70
10
5
1/2 tCLKIN
2.5 tCLKIN
31.25
27.78
3.47
kHz min
MHz max
MHz max
ns min
ns max
µs max
µs max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ms typ
ms typ
ms typ
Master Clock Frequency
L Version
CONVST Pulse Width
CONVST to BUSY ↑ Propagation Delay
Conversion Time = 18 tCLKIN
L Version 1.8 MHz CLKIN. Conversion Time = 18 tCLKIN
HBEN to RD Setup Time
HBEN to RD Hold Time
CS to RD to Setup Time
CS to RD Hold Time
RD Pulse Width
Data Access Time After RD
Bus Relinquish Time After RD
Bus Relinquish Time After RD
Minimum Time Between Reads
HBEN to WR Setup Time
HBEN to WR Hold Time
CS to WR Setup Time
CS to WR Hold Time
WR Pulse Width
Data Setup Time Before WR
Data Hold Time After WR
New Data Valid Before Falling Edge of BUSY
CS ↑ to BUSY ↑ in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent (125013
tCLKIN)
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111124 tCLKIN)
System Offset Calibration Time, Master Clock Dependent
(13889 tCLKIN)
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.
3The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-
Down section).
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5t9 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 9, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8 MHz master clock.
Specifications subject to change without notice.
–4–
REV. A
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