AT25640B(2010) 查看數據表（PDF） - Atmel Corporation
零件编号
产品描述 (功能)
生产厂家
AT25640B Datasheet PDF : 26 Pages
| |||
Atmel AT25320B/640B
3. Functional Description
The Atmel® AT25320B/640B is designed to interface directly with the synchronous serial peripheral interface (SPI)
of the 6805 and 68HC11 series of microcontrollers.
The AT25320B/640B utilizes an 8-bit instruction register. The list of instructions and their operation codes are con-
tained in Table 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-
low CS transition.
Table 3-1. Instruction Set for the Atmel AT25320B/640B
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All program-
ming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly,
the Block Write Protection Bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 3-2.
Bit 7
WPEN
Status Register Format
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Table 3-3. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle
is in progress.
Bit 1 (WEN)
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the
device is write enabled.
Bit 2 (BP0)
See Table 3-4 on page 8.
Bit 3 (BP1)
See Table 3-4 on page 8.
Bits 4–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 3-5 on page 8.
Bits 0–7 are “1”s during an internal write cycle.
7
8535F–SEEPR–6/10
Share Link: 