AT25DF641 查看數據表（PDF） - Atmel Corporation

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产品描述 (功能)

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AT25DF641

64-Megabit 2.7-volt Minimum SPI Serial Flash Memory

Atmel Corporation 

3. Block Diagram

Figure 3-1. Block Diagram

CS

SCK

SI (SIO)

SO (SOI)

WP

HOLD

INTERFACE

CONTROL

AND

LOGIC

AT25DF641 [Preliminary]

CONTROL AND

PROTECTION LOGIC

Y-DECODER

X-DECODER

I/O BUFFERS

AND LATCHES

SRAM

DATA BUFFER

Y-GATING

FLASH

MEMORY

ARRAY

4. Memory Array

To provide the greatest flexibility, the memory array of the AT25DF641 can be erased in four lev-

els of granularity including a full chip erase. In addition, the array has been divided into physical

sectors of uniform size, of which each sector can be individually protected from program and

erase operations. The size of the physical sectors is optimized for both code and data storage

applications, allowing both code and data segments to reside in their own isolated regions. The

Memory Architecture Diagram illustrates the breakdown of each erase level as well as the

breakdown of each physical sector.

5

3680E–DFLASH–12/08

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