AT29C256-15 查看數據表（PDF） - Atmel Corporation

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AT29C256-15

256K 32K x 8 5-volt Only CMOS Flash Memory

Atmel Corporation 

AT29C256

Device Operation (Continued)

Once set, software data protection will remain active un-

less the disable command sequence is issued.

After setting SDP, any attempt to write to the device with-

out the 3-byte command sequence will start the internal

write timers. No data will be written to the device; however,

for the duration of tWC, a read operation will effectively be

a polling operation.

After the software data protection’s 3-byte command code

is given, a byte load is performed by applying a low pulse

on the WE or CE input with CE or WE low (respectively)

and OE high. The address is latched on the falling edge of

CE or WE, whichever occurs last. The data is latched by

the first rising edge of CE or WE. The 64-bytes of data

must be loaded into each sector by the same procedure as

outlined in the program section under device operation.

HARDWARE DATA PROTECTION: Hardware features

protect against inadvertent programs to the AT29C256 in

the following ways: (a) VCC sense— if VCC is below 3.8V

(typical), the program function is inhibited. (b) VCC power

on delay— once VCC has reached the VCC sense level,

the device will automatically time out 5 ms (typical) before

programming. (c) Program inhibit— holding any one of OE

low, CE high or WE high inhibits program cycles. (d) Noise

filter— pulses of less than 15 ns (typical) on the WE or CE

inputs will not initiate a program cycle.

PRODUCT IDENTIFICATION: The product identifica-

tion mode identifies the device and manufacturer and may

be accessed by a hardware operation. For details, see

Operating Modes or Product Identification.

DATA POLLING: The AT29C256 features DATA poll-

ing to indicate the end of a program cycle. During a pro-

gram cycle an attempted read of the last byte loaded will

result in the complement of the loaded data on I/O7. Once

the program cycle has been completed, true data is valid

on all outputs and the next cycle may begin. DATA polling

may begin at any time during the program cycle.

TOGGLE BIT: I n a d d i t i o n t o DATA p o l l i n g t h e

AT29C256 provides another method for determining the

end of a program or erase cycle. During a program or

erase operation, successive attempts to read data from

the device will result in I/O6 toggling between one and

zero. Once the program cycle has completed, I/O6 will

stop toggling and valid data will be read. Examining the

toggle bit may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE: The entire device

can be erased by using a 6-byte software code. Please

see Software Chip Erase application note for details.

Absolute Maximum Ratings*

Temperature Under Bias................. -55°C to +125°C

Storage Temperature...................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to VCC + 0.6V

Voltage on OE

with Respect to Ground ................... -0.6V to +13.5V

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at these or any other conditions beyond those indi-

cated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

4-95

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