AT48802-16QC 查看數據表（PDF） - Atmel Corporation

零件编号

产品描述 (功能)

生产厂家

AT48802-16QC

Spread-Spectrum Signal Processor Integrated Circuit

Atmel Corporation 

Data Bus Read Cycle Timing

The READ cycle’s multiplexed addressing scheme is the

same as the WRITE cycle. Address mapping is also simi-

larly made to the lower-order address bits. That is, register

0 has an address code of HEX 00, while register A has an

address code of HEX 0A. Data will be valid on the data

bus and RD signal latches data as it goes from a low to a

high state. The timing is shown in Figure 5 below.

Figure 5. Read Cycle Timing Diagram

Internal Data Path

The AT48802 has a 234 bits per second synchronous full

duplex internal data path. This uses in-band signaling by

Manchester coded BPSK modulating an 1875 Hz carrier,

so voice must be disabled when data is on. This path is

intended for call setup and control functions.

To transmit data, R6 b6 (TDE transmit data enable) must

be set. The data presented to the TX DATA pin 49 will be

transmitted out of the ME DOUT pin 20. The input data

must be synchronized, and this can be achieved by using

the DITHER pin 54 as a clock. When transmission is com-

plete the TDE bit should be reset.

To receive data, R6 b5 (RDE receive data enable) must be

set. The CARRIER output pin 17 will indicate when valid

data is available. The ME DATA IN pin 23 must be pre-

sented with a digital signal; an analog signal would have to

be sent through a comparator with the correct amount of

hysteresis first. The RX DATA pin 53 has the received

data on it for use by the microcontroller. When reception is

complete then R6 b5 should be reset.

The data receiver has fully adjustable internal timing to ac-

commodate the delays of various RF designs.

2-10

AT48802

Share Link: