AT49F040A 查看數據表（PDF） - Atmel Corporation

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AT49F040A

4-megabit (512K x 8) 5-volt Only Flash Memory

Atmel Corporation 

3. Block Diagram

VCC

GND

OE

WE

CE

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

AT49F040A

AT49F040A

DATA INPUTS/OUTPUTS

I/O7 - I/O0

8

INPUT/OUTPUT

BUFFERS

PROGRAM

DATA LATCHES

Y-GATING

MAIN MEMORY

BLOCK 8

(64K BYTES)

MAIN MEMORY

BLOCK 7

(64K BYTES)

MAIN MEMORY

BLOCK 6

(64K BYTES)

MAIN MEMORY

BLOCK 5

(64K BYTES)

MAIN MEMORY

BLOCK 4

(64K BYTES)

MAIN MEMORY

BLOCK 3

(64K BYTES)

MAIN MEMORY

BLOCK 2

(64K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

PARAMETER

BLOCK 2

(8K BYTES)

PARAMETER

BLOCK 1

(8K BYTES)

BOOT BLOCK

(16K BYTES)

7FFFF

70000

6FFFF

60000

5FFFF

50000

4FFFF

40000

3FFFF

30000

2FFFF

20000

1FFFF

10000

0FFFF

08000

07FFF

06000

05FFF

04000

03FFF

00000

4. Device Operation

4.1 Read

The AT49F040A is accessed like an EPROM. When CE and OE are low and WE is high, the

data stored at the memory location determined by the address pins is asserted on the outputs.

The outputs are put in the high impedance state whenever CE or OE is high. This dual-line con-

trol gives designers flexibility in preventing bus contention.

3

3359D–FLASH–3/05

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