AT80C51RD2-RLRUM 查看數據表（PDF） - Atmel Corporation

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AT80C51RD2-RLRUM

80C51 High Performance ROM 8-bit Microcontroller

Atmel Corporation 

Oscillators

Overview

Registers

Prescaler Divider

AT80C51RD2/AT83C51Rx2

One oscillator is available for CPU:

• OSC used for high frequency (3 MHz to 40 MHz)

In order to optimize the power consumption and the execution time needed for a specific

task, an internal prescaler feature has been implemented between the selected oscilla-

tor and the CPU.

Table 4. Clock Reload Register

7

6

5

4

3

2

1

0

-

-

-

-

-

-

-

-

Bit

Bit

Number Mnemonic Description

7:0

CKRL Clock Reload Register: Prescaler value

Reset Value = 1111 1111b

Not bit addressable

A hardware RESET puts the prescaler divider in the following state:

• CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature)

KS signal selects OSC: FCLK OUT = FOSC

• Any value between FFh down to 00h can be written by software into CKRL register

in order to divide frequency of the selected oscillator:

– CKRL = 00h: minimum frequency

FCLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode)

FCLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode)

– CKRL = FFh: maximum frequency

FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)

FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)

– FCLK CPU and FCLK PERIPH

In X2 mode:

FCPU = FCLKPERIPH = 2-----×-----(---2---5-F--5--O---–-S---C-C----K----R----L----)

In X1 mode:

FCPU = FCLKPERIPH = 4-----×-----(---2--F-5---5-O---S-–--C---C-A---K----R----L-----)

9

4113B–8051–03/05

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