AT88SC018 查看數據表（PDF） - Atmel Corporation

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AT88SC018

CryptoCompanion™ Chip for CryptoMemory and CryptoRF

Atmel Corporation 

CryptoCompanion™ Chip

1.3. Package, Pin Definition & IO

1.3.1. Pin Definition

1.3.1.1. VCC , Gnd

Power supply is 2.7 – 3.6V. Supply current less than 5 mA.

CryptoCompanion will be available to accept commands 60 ms after the later of VCC rising above 2.7V or Reset being

driven high if CryptoCompanion is in a security delay then this interval is significantly longer.

During Power Up, VCC must exhibit a monotonic ramp at a minimum rate of 50 mV/mS until VCC has crossed the 2.7V

level. During Power Down, VCC must exhibit a monotonic ramp at a minimum rate of 50 mV/mS once it has dropped

below the 2.5V boundary. CryptoCompanion does not support hot swapping or hot plugging.

VCC must be bypassed with high quality surface mount capacitors that are properly located on the board. Atmel

recommends two capacitors connected in parallel having a value of 1μF and 0.01μF. The capacitors should be

manufactured using X5R or X7R dielectric material. These capacitors should be connected to CryptoCompanion using

a total of no more than 1cm PC board traces. Atmel recommends the use of a ground plane and a trace length of less

than 0.5cm between the capacitors and the VCC pin. Failure to follow these recommendations may result in improper

operation.

1.3.1.2. SDA

Two wire interface data pin, 5 V compatible. Minimum data setup time = 0.1 μs, and minimum data hold time = 0 μs min.

The system board must include an external pull-up resistor.

1.3.1.3. SCL

Two wire interface clock pin, 5 V compatible. Maximum SCL rate is 400KHz, minimum TLOW = 1.2 μs, minimum

THIGH = 0.6 μs. The system board must include an external pull-up resistor.

1.3.1.4. Reset (RST)

This active low input will reset all states within CryptoCompanion. Honored regardless of the state of PowerDown.

1.3.1.5. PowerDown (PDN)

When held low, the part operates normally. When held high the part will go to sleep and ignore all transitions on SDA

and SCL, power consumption will drop to less than 10 μA. There is a 50 ms delay between this pin falling and the first

transition on SDA or SCL that will be accepted by the chip.

3

5277DS–CryptoCompanion–9/09

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