AT89C2051X2-16PC 查看數據表（PDF） - Atmel Corporation

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AT89C2051X2-16PC

8-bit Microcontroller with 2K Bytes Flash

Atmel Corporation 

Restrictions on

Certain Instructions

Branching Instructions

MOVX-related Instructions,

Data Memory

The AT89C2051x2 is an economical and cost-effective member of Atmel’s growing fam-

ily of microcontrollers. It contains 2K bytes of Flash program memory. It is fully

compatible with the MCS-51 architecture, and can be programmed using the MCS-51

instruction set. However, there are a few considerations one must keep in mind when

utilizing certain instructions to program this device.

All the instructions related to jumping or branching should be restricted such that the

destination address falls within the physical program memory space of the device, which

is 2K for the AT89C2051x2. This should be the responsibility of the software program-

mer. For example, LJMP 7E0H would be a valid instruction for the AT89C2051x2 (with

2K of memory), whereas LJMP 900H would not.

LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR

These unconditional branching instructions will execute correctly as long as the pro-

grammer keeps in mind that the destination branching address must fall within the

physical boundaries of the program memory size (locations 00H to 7FFH for the

AT89C2051x2). Violating the physical space limits may cause unknown program

behavior.

CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ

With these conditional branching instructions, the same rule above applies. Again, vio-

lating the memory boundaries may cause erratic execution.

For applications involving interrupts, the normal interrupt service routine address loca-

tions of the 80C51 family architecture have been preserved.

The AT89C2051x2 contains 128 bytes of internal data memory. Thus, in the

AT89C2051x2, the stack depth is limited to 128 bytes, the amount of available RAM.

External DATA memory access is not supported in this device, nor is external PRO-

GRAM memory execution. Therefore, no MOVX [...] instructions should be included in

the program.

A typical 80C51 assembler will still assemble instructions, even if they are written in vio-

lation of the restrictions mentioned above. It is the responsibility of the controller user to

know the physical features and limitations of the device being used and adjust the

instructions used correspondingly.

Program Memory

Lock Bits

On the chip are two lock bits which can be left unprogrammed (U) or can be pro-

grammed (P) to obtain the additional features listed in the table below:

Lock Bit Protection Modes(1)

Program Lock Bits

LB1

LB2

Protection Type

1

U

U

No program lock features.

2

P

U

Further programming of the Flash is disabled.

3

P

P

Same as mode 2, also verify is disabled.

Note: 1. The Lock Bits can only be erased with the Chip Erase operation.

6 AT89C2051x2

3285B–MICRO–10/03

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