AT93C46A-10SU-2.7 查看數據表（PDF） - Atmel Corporation
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AT93C46A-10SU-2.7 Datasheet PDF : 15 Pages
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Figure 6. WRITE Timing
CS
tCS
SK
DI
1
0
1
AN
...
A0 DN
... D0
DO
HIGH IMPEDANCE
BUSY
tWP
READY
Figure 7. WRAL Timing(1 ),( 2 )
CS
SK
DI
1
0
0
0
1
...
DO
HIGH IMPEDANCE
Notes: 1. Valid only at VCC = 4.5V to 5.5V.
2. Requires a minimum of nine clock cycles.
Figure 8. ERASE Timing
CS
SK
DI
111
AN AN-1 AN-2 ...
A0
DO
HIGH IMPEDANCE
tCS
DN ... D0
BUSY
tWP
READY
tCS
CHECK
STATUS
STANDBY
tWP
tSV
BUSY
READY
tDF
HIGH IMPEDANCE
8 AT93C46A
0539K–SEEPR–2/07
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