ATMEGA6450V-8AJ 查看數據表（PDF） - Atmel Corporation
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ATMEGA6450V-8AJ Datasheet PDF : 347 Pages
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ATmega325/3250/645/6450
The X-register, Y-register, and The registers R26..R31 have some added functions to their general purpose usage.
Z-register
These registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 6.
Figure 6. The X-, Y-, and Z-registers
15
XH
XL
0
X-register
7
07
0
R27 (0x1B)
R26 (0x1A)
Stack Pointer
15
YH
YL
0
Y-register
7
07
0
R29 (0x1D)
R28 (0x1C)
Z-register
15
ZH
7
0
R31 (0x1F)
ZL
0
7
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed dis-
placement, automatic increment, and automatic decrement (see the instruction set
reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for
storing return addresses after interrupts and subroutine calls. The Stack Pointer Regis-
ter always points to the top of the Stack. Note that the Stack is implemented as growing
from higher memory locations to lower memory locations. This implies that a Stack
PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter-
rupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above 0x60. The Stack Pointer is decremented by one
when data is pushed onto the Stack with the PUSH instruction, and it is decremented by
two when the return address is pushed onto the Stack with subroutine call or interrupt.
The Stack Pointer is incremented by one when data is popped from the Stack with the
POP instruction, and it is incremented by two when data is popped from the Stack with
return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num-
ber of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
Bit
Read/Write
Initial Value
15
14
13
12
11
10
9
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP7
SP6
SP5
SP4
SP3
SP2
SP1
7
6
5
4
3
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
SP8
SP0
0
R/W
R/W
0
0
SPH
SPL
13
2570A–AVR–09/04
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