ATMEGA64A-MN(2013) 查看數據表（PDF） - Atmel Corporation

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ATMEGA64A-MN
(Rev.:2013)

8-bit Atmel Microcontroller with 64KB In-System Programmable Flash

Atmel Corporation 

for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,

described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single

register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated

to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the

whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address

contains a 16-bit or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot program section and the Application program

section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes

into the Application Flash memory section must reside in the Boot program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack

is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total

SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before sub-

routines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data

SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in

the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have

priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the

priority.

The I/O memory space contains 64 addresses which can be accessed directly, or as the Data Space locations fol-

lowing those of the Register File, 0x20 - 0x5F. In addition, the ATmega64A has Extended I/O space from 0x60 -

0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

7.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.

Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an

immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-

functions. Some implementations of the architecture also provide a powerful multiplier supporting both

signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

7.3 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This

information can be used for altering program flow in order to perform conditional operations. Note that the Status

Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases

remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning

from an interrupt. This must be handled by software.

7.3.1 SREG – AVR Status Register

Bit

7

6

5

4

3

2

1

0

0x3F (0x5F)

I

T

H

S

V

N

Z

C

SREG

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

ATmega64A [DATASHEET]

9

8160D–AVR–02/2013

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