ATTINY40 查看數據表（PDF） - Atmel Corporation
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ATTINY40 Datasheet PDF : 216 Pages
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ATtiny40
5. Memories
This section describes the different memories in the ATtiny40. The device has two main memory
areas, the program memory space and the data memory space.
5.1 In-System Re-programmable Flash Program Memory
The ATtiny40 contains 4K byte on-chip, in-system reprogrammable Flash memory for program
storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 2048 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny40 Pro-
gram Counter (PC) is 11 bits wide, thus capable of addressing the 2048 program memory
locations, starting at 0x000. “Memory Programming” on page 156 contains a detailed description
on Flash data serial downloading.
Constant tables can be allocated within the entire address space of program memory. Since pro-
gram memory can not be accessed directly, it has been mapped to the data memory. The
mapped program memory begins at byte address 0x4000 in data memory (see Figure 5-1 on
page 16). Although programs are executed starting from address 0x000 in program memory it
must be addressed starting from 0x4000 when accessed via the data memory.
Internal write operations to Flash program memory have been disabled and program memory
therefore appears to firmware as read-only. Flash memory can still be written to externally but
internal write operations to the program memory area will not be succesful.
Timing diagrams of instruction fetch and execution are presented in “Instruction Execution Tim-
ing” on page 10.
5.2 Data Memory
Data memory locations include the I/O memory, the internal SRAM memory, the non-volatile
memory lock bits, and the Flash memory. See Figure 5-1 on page 16 for an illustration on how
the ATtiny40 memory space is organized.
The first 64 locations are reserved for I/O memory, while the following 256 data memory loca-
tions (from 0x0040 to 0x013F) address the internal data SRAM.
The non-volatile memory lock bits and all the Flash memory sections are mapped to the data
memory space. These locations appear as read-only for device firmware.
The four different addressing modes for data memory are direct, indirect, indirect with pre-decre-
ment, and indirect with post-increment. In the register file, registers R26 to R31 function as
pointer registers for indirect addressing.
The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using
the LDS and STS instructions reaches the lowest 128 locations between 0x0040 and 0x00BF.
The indirect addressing reaches the entire data memory space. When using indirect addressing
modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are
decremented or incremented.
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8263A–AVR–08/10
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