ATTINY40 查看數據表（PDF） - Atmel Corporation
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ATTINY40 Datasheet PDF : 216 Pages
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ATtiny40
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers contain-
ing such status flags. The CBI and SBI instructions work on registers in the address range 0x00
to 0x1F, only.
The I/O and Peripherals Control Registers are explained in later sections.
5.4 Register Description
5.4.1
RAMAR – RAM Address Register
Bit
0x20
Read/Write
Initial Value
7
RAMAR7
R/W
X
6
RAMAR6
R/W
X
5
RAMAR5
R/W
X
4
RAMAR4
R/W
X
3
RAMAR3
R/W
X
2
RAMAR2
R/W
X
1
RAMAR1
R/W
X
0
RAMAR0
R/W
X
RAMAR
• Bits 7:0 – RAMAR[7:0]: RAM Address
The RAMAR register contains the RAM address bits. The RAM data bytes are addressed lin-
early in the range 0..255. The initial value of RAMAR is undefined and a proper value must be
therefore written before the RAM may be accessed.
5.4.2
RAMDR – RAM Data Register
Bit
0x1F
Read/Write
Initial Value
7
RAMDR7
R/W
X
6
RAMDR6
R/W
X
5
RAMDR5
R/W
X
4
RAMDR4
R/W
X
3
RAMDR3
R/W
X
2
RAMDR2
R/W
X
1
RAMDR1
R/W
X
0
RAMDR0
R/W
X
RAMDR
• Bits 7:0 – RAMDR[7:0]: RAM Data
For the RAM write operation, the RAMDR register contains the RAM data to be written to the
RAM in address given by the RAMAR register. For the RAM read operation, the RAMDR con-
tains the data read out from the RAM at the address given by RAMAR.
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8263A–AVR–08/10
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