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ATTINY40 查看數據表(PDF) - Atmel Corporation

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ATTINY40 Datasheet PDF : 216 Pages
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1. Pin Configurations
Figure 1-1. Pinout of ATtiny40
SOIC/TSSOP
(PCINT8/ADC8) PB0 1
(PCINT7/ADC7) PA7 2
(PCINT6/ADC6) PA6 3
(PCINT5/ADC5/OC0B) PA5 4
(PCINT4/ADC4/T0) PA4 5
(PCINT3/ADC3) PA3 6
(PCINT2/ADC2/AIN1) PA2 7
(PCINT1/ADC1/AIN0) PA1 8
(PCINT0/ADC0) PA0 9
GND 10
20 PB1 (ADC9/PCINT9)
19 PB2 (ADC10/PCINT10)
18 PB3 (ADC11/PCINT11)
17 PC0 (OC0A/SS/PCINT12)
16 PC1 (SCK/SCL/ICP1/T1/PCINT13)
15 PC2 (INT0/CLKO/MISO/PCINT14)
14 PC3 (RESET/PCINT15)
13 PC4 (MOSI/SDA/TPIDATA/PCINT16)
12 PC5 (CLKI/TPICLK/PCINT17)
11 VCC
MLF/VQFN
(PCINT6/ADC6) PA6 1
(PCINT5/ADC5/OC0B) PA5 2
(PCINT4/ADC4/T0) PA4 3
(PCINT3/ADC3) PA3 4
(PCINT2/ADC2/AIN1) PA2 5
15 PC0 (OC0A/SS/PCINT12)
14 PC1 (SCK/SCL/ICP1/T1/PCINT13)
13 PC2 (INT0/CLKO/MISO/PCINT14)
12 PC3 (RESET/PCINT15)
11 PC4 (MOSI/SDA/TPIDATA/PCINT16)
NOTE: Bottom pad should be soldered to ground.
1.1 Pin Description
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The min-
imum pulse length is given in Table 21-4 on page 168. Shorter pulses are not guaranteed to
generate a reset.
The reset pin can also be used as a (weak) I/O pin.
2 ATtiny40
8263A–AVR–08/10

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