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ATTINY40 查看數據表(PDF) - Atmel Corporation

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ATTINY40 Datasheet PDF : 216 Pages
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2. Overview
ATtiny40 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny40
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
Figure 2-1. Block Diagram
VCC
RESET
PROGRAMMING
LOGIC
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
ISP
INTERFACE
PROGRAM
COUNTER
STACK
POINTER
SRAM
INTERRUPT
UNIT
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
RESET FLAG
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
TIMER/
COUNTER1
SPI
TWI
8-BIT DATA BUS
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
ANALOG
COMPARATOR
ADC
DATA REGISTER
PORT A
DIRECTION
REG. PORT A
DATA REGISTER
PORT B
DIRECTION
REG. PORT B
DATA REGISTER
PORT C
DIRECTION
REG. PORT C
DRIVERS
PORT A
DRIVERS
PORT B
DRIVERS
PORT C
PA[7:0]
PB[3:0]
PC[5:0]
GND
The AVR core combines a rich instruction set with 16 general purpose working registers and
system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock cycle.
4 ATtiny40
8263A–AVR–08/10

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