ATTINY861/V 查看數據表（PDF） - Atmel Corporation
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ATTINY861/V Datasheet PDF : 236 Pages
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6.5.2
EEDR – EEPROM Data Register
Bit
0x1D (0x3D)
Read/Write
Initial Value
7
EEDR7
R/W
0
6
EEDR6
R/W
0
5
EEDR5
R/W
0
4
EEDR4
R/W
0
3
EEDR3
R/W
0
2
EEDR2
R/W
0
1
EEDR1
R/W
0
0
EEDR0
R/W
0
EEDR
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
6.5.3
EECR – EEPROM Control Register
Bit
7
6
0x1C (0x3C)
–
–
Read/Write
R
R
Initial Value
0
0
5
EEPM1
R/W
X
4
EEPM0
R/W
X
3
EERIE
R/W
0
2
EEMPE
R/W
0
1
EEPE
R/W
X
0
EERE
R/W
0
EECR
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use and will always read as 0 in ATtiny261/461/861. For compati-
bility with future AVR devices, always write this bit to zero. After reading, mask out this bit.
• Bit 6 – Res: Reserved Bit
This bit is reserved in the ATtiny261/461/861 and will always read as zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bits setting defines which programming action that will be
triggered when writing EEPE. It is possible to program data in one atomic operation (erase the
old value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in Table 6-1. While EEPE
is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00
unless the EEPROM is busy programming.
Table 6-1. EEPROM Mode Bits
EEPM1 EEPM0
Programming
Time
0
0
3.4 ms
0
1
1.8 ms
1
0
1.8 ms
1
1
–
Operation
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
Reserved for future use
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-
rupt when Non-volatile memory is ready for programming.
22 ATtiny261/461/861
2588B–AVR–11/06
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