ATV750B-15JI(2001) 查看數據表（PDF） - Atmel Corporation

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ATV750B-15JI
(Rev.:2001)

High-speed UV Erasable Programmable Logic Device

Atmel Corporation 

Preload of

Registered

Outputs

ATV750B(L)

The ATV750B(L) registers are provided with circuitry to allow loading of each register asyn-

chronously with either a high or a low. This feature will simplify testing since any state can be

forced into the registers to control test sequencing. A VIH level on the I/O pin will force the reg-

ister high; a VIL will force it low, independent of the output polarity. The PRELOAD state is

entered by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When

the clock term is pulsed high, the data on the I/O pins is placed into the register chosen by the

Select Pin.

Level Forced on Registered

Output Pin during

PRELOAD Cycle

VIH

VIL

VIH

VIL

Select Pin

State

Low

Low

High

High

Register #0 State after

Cycle

High

Low

X

X

Register #1 State after

Cycle

X

X

High

Low

9

0301I–08/01

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