HSP48901JC-20 查看數據表（PDF） - Intersil
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HSP48901JC-20 Datasheet PDF : 9 Pages
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HSP48901
AC Electrical Specifications VCC = 5.0V ±5%, TA = 0oC to 70oC
PARAMETER
SYMBOL NOTES
TEST
CONDITIONS
-30
MIN
MAX
-40
MIN
MAX
UNITS
Address Hold Time
tAH
2
-
2
-
ns
Configuration Data Setup Time
tCS
10
-
12
-
ns
Configuration Data Hold Time
tCH
0
-
0
-
ns
LD Pulse Width
tLPH
13
-
20
-
ns
LD Setup Time
tLCS
Note 4
31
tCYCLE+2
40
tCYCLE+2
ns
HOLD Setup Time
tHS
10
-
12
-
ns
HOLD Hold Time
tHH
0
-
0
-
ns
FRAME Pulse Width
tFPW
tCYCLE
-
tCYCLE
-
ns
FRAME Setup Time
tFS
Note 5
28
-
40
-
ns
Output Rise
tR
From 0.8V to 2.0V
-
8
-
8
ns
Output Fall Time
tF
From 2.0V to 0.8V
-
8
-
8
ns
NOTES:
4. This specification applies only to the case where a change in the active Coefficient Register is being selected during a convolution operation. It must
be met in order to achieve predictable results at the next rising clock edge. In most applications, this selection will be made asynchronously, and the
tLCS Specification may be disregarded.
5. While FRAME is asynchronous with respect to CLK, it must be deasserted a minimum of tFS ns prior to the rising clock edge which is to begin loading
new pixel data for the next frame.
6. AC Testing is performed as follows: Input levels (CLK Input) = 4.0V and 0V; input levels (all other inputs) = 0V to 3.0V; input timing reference levels:
(CLK) = 2.0V, (others) = 1.5V; other timing references: VOH ≥ 1.5V, VOL ≤ 1.5V; output load test load circuit with CL = 40pF.
Test Load Circuit
S1
DUT
(NOTE 7) CL
NOTES:
7. Includes stray and jig capacitance.
8. Switch S1 Open for ICCSB and ICCOP Tests.
IOH
± 1.5V
IOL
EQUIVALENT CIRCUIT
8
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