LB1922 查看數據表（PDF） - SANYO -> Panasonic

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LB1922

Three-Phase Brushless Motor Driver for Office Automation Applications

SANYO -> Panasonic 

LB1922

LB1922 Functional Description and Notes on External Components

1. Speed control circuit

Speed control in this IC is implemented with the combination of a speed discriminator circuit and a PLL circuit. The

speed discriminator circuit outputs an error output once every two FG periods using a charge pump technique. The

PLL circuit outputs a phase error once every FG period, also using a charge pump technique. As compared to the

earlier technique of only using a speed discriminator circuit, the combination of a speed discriminator circuit and a

PLL circuit is better able to suppress speed fluctuations when used in situations where large load variations are

applied to the motor. Since the FG servo frequency is determined by the following formula, applications must

determine the motor speed by setting the number of FG pulses and the crystal oscillator frequency.

fFG(servo) = fOSC/8192

fOSC: The crystal oscillator frequency

2. Direct PWM drive

To minimize power loss in the output, this IC adopts a direct PWM drive technique. The output transistors are always

saturated when on, and motor drive is adjusted by changing the duty with which the output transistors are on. Since

the output switching is performed by the lower side transistors, Schottky diodes (D1, D2, and D3) or similar devices

must be connected between OUT and VCC. (This is because if the devices used do not have a short reverse recovery

time, through currents will flow at the instant the lower side transistors turn on.) Normal rectifying diodes can be used

between OUT and ground.

3. Current limiter circuit

The current limiter circuit operates at a current determined by the formula I = 0.5/Rf, and operates as a peak current

limiter. Its current limiting operation consists of reducing the duty with which the output is on to suppress the current

drawn. No phase compensation capacitors are required.

4. Speed lock range

The speed lock range is ±6.25% of the set speed. When the motor speed is in the lock range the LD pin goes low.

(The LD pin is an open-collector output.) If the motor speed goes out of the lock range, the motor drive output on

duty is modified according to the speed error. This controls the motor speed to be in the lock range.

5. PWM frequency

The PWM frequency is determined by the resistor (R3) and the capacitor (C6) connected to the CR pin.

• If R3 is connected to the 4-V fixed-voltage supply:

fPWM ≈ 1/(1.2 × C × R)

• If R3 is connected to the 7-V fixed-voltage supply:

fPWM ≈ 1/(0.5 × C × R)

Do not use a value of 30 kΩ or less for R3. A PWM frequency of about 15 kHz is desirable. If the PWM frequency is

too low, the motor may resonate at the PWM frequency during motor constraint, and if the PWM frequency is in the

audible range result in noise. Inversely, if the PWM frequency is too high, the loss in the output transistors during

switching will increase.

6. Ground leading

GND1 (pin 22) --- Ground for all circuits other than the output block

GND2 (pin 11) --- Output block ground (the sink transistor emitter)

D4, D5, and D6 must be connected to GND2. All other external components must be connected to GND1. A single

ground point must be taken for GND1 and GND2 at the connector. Since GND2 carries large currents, the GND2

lines must be kept as short as possible.

7. Parasitic effects in the output

Parasitic effects occur when the output pin voltage falls –0.7 V below the GND1 and GND2 potential. (Note that the

actual value may become smaller than –0.7 V due to device temperature characteristics.) Also, applications must be

designed so that the output pin voltage never exceeds VCC by 1 V or more. If a parasitic effect occurs, at first speed

control will be lost intermittently. If the parasitic effects increase, the output transistors may be destroyed. Since D1,

No. 5679-5/10

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