BD5446EFV 查看數據表（PDF） - ROHM Semiconductor

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BD5446EFV

Class-D Speaker Amplifier or Digital Input

ROHM Semiconductor 

BD5446EFV

●Audio Interface format and timing

Recommended timing and operating conditions (MCLK, BCLK, LRCLK, SDATA)

1/ｆ SYS_CLK

SYS_CLK

LRCLK

1/ fLRCLK

BCLK

1/fBCLK

Fig-26 Clock timing

Technical Note

LRCLK

BCLK

tHD;LR

tSU;LR

tSU ; SD

tHD ; SD

SDATA

Fig-27 Audio Interface timing (1)

SYS_CLK

tHD ; BC

tSU ; BC

BCLK

Fig-28 Audio Interface timing (2)

Parameter

Symbol

Limit

Min.

Max.

1 SYS_CLK frequency

fSYS_CLK

8.192

12.288

2 LRCLK frequency

fLRCLK

32

48

3 BCLK frequency

fBCLK

2.048

3.072

4 Setup time, LRCLK※1

tSU;LR

20

－

5 Hold time, LRCLK※1

tHD;LR

20

－

6 Setup time, SDATA

tSU;SD

20

－

7 Hold time, SDATA

tHD;SD

20

－

8 Setup time, BCLK※2

tSU;BC

2.5

－

9 Hold time, BCLK※2

tHD;BC

3.5

－

※1 This regulation is to keep rising edge of LRCK and rising edge of BCLK from overlapping.

※2 This regulation is to keep rising edge of SYS_CLK and rising edge of BCLK from overlapping.

Unit

MHz

kHz

MHz

ns

ns

ns

ns

ns

ns

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© 2011 ROHM Co., Ltd. All rights reserved.

14/31

2011.06 - Rev.C

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