BD8381EFV-M 查看數據表（PDF） - ROHM Semiconductor
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BD8381EFV-M Datasheet PDF : 21 Pages
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BD8381EFV-M
●Block diagram and pin configuration
Technical Note
Vin
VREG
FAIL1
VCC
VREG
UVLO TSD
OVP
OCP
OVP
CS
EN
SYNC
RT
COMP
VREG
SS
THM
DRLIN
VREG
DISC
VTH
PWM
Timer
Latch
Control Logic
OSC
SLOPE
PWM
OCP OVP
SS
ERR AMP
-
+
+
DRV
CTL
VREG
SHORT
Det
BOOT
OUTH
SW
DGND
OUTL
GND
LEDR
LEDC
PWMOUT
FB
CR
TIMER
OPEN/ SHORT/ SCP Detect
Timer
Latch
Open Det
SCP Det
FAIL2
PGND
CT
COUT
●Pin layout
BD8381EFV-M(HTSSOP-B28)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Fig.11
Fig.10 Buck-boost application composition
●Pin function table
Pin
Symbol
Function
1
COMP Error amplifier output
2
SS
Soft start
3
VCC
Input power supply
28
4
EN
Enable input
5
RT
Oscillation frequency-setting resistance input
27
6
SYNC External synchronization signal input
26
7
GND
Small-signal GND
25
8
THM
Thermally sensitive resistor connection pin
24
9
FB
ERRAMP FB signal input pin
10
DISC
CR Timer discharge pin
23
11
VTH
CR Timer threshold pin
22
12
DRLIN DRL switch terminal (Pulse output setting terminal)
21
13
FAIL1
Failure signal output
20
14
FAIL2
LED open/short detection signal output
19
15
OVP
Over-voltage detection input
16
LEDC
LED short detection pin (LED detection side)
18
17
LEDR
LED short detection pin (Resistor detection side)
17
18
N.C.
-
16
19
PGND PWM brightness source pin
15
20 PWMOUT PWM brightness signal output pin
21
CT
GND short protection timer setting pin
22
OUTL
Low-side external FET Gate Drive out put
23
DGND Low-side FET driver source pin
24
SW
High-side FET Source pin
25
OUTH High-side external FET Gate Drive out put
26
CS
DC/DC output current detection pin
27
BOOT High-side FET driver source pin
28
VREG Internal reference voltage output
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4/20
2011.04 - Rev.A
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