BD8381EFV-M
Technical Note
●Error all condition
Protection
UVLO
Detecting Condition
[Detect]
VREG<4.3V
[Release]
VREG>4.45V
TSD
Tj>175℃
Tj<150℃
OVP
VOVP>2.0V
VOVP<1.45V
OCP
SCP
LED open
LED short
VCS≦VCC-0.6V
VFB<0.05V
(150ms delay when CT=0.1µF)
VFB<0.05V & VOVP>1.7V
lVLEDR-VLEDCl>0.2V
(100ms delay when FOSC=300kHz)
VCS>VCC-0.6V
EN or UVLO
EN or UVLO
EN or UVLO
Operation after detect
All blocks (but except REG)
shut down
All blocks (but except REG)
shut down
SS discharged
SS discharged
Counter starts and then latches off
all blocks (but except REG)
Counter starts and then latches off
all blocks (but except REG)
Counter starts and then latches off
all blocks (but except REG)
●Protection sequence
Vcc
EN
①
VREG
UVLO
THM
(Input by the
resistance division
of VREG. )
SYNC
DRLIN
SS
OUTL
VOUT
4.5V
Release
②
②
②
Fig.17
Power supply turning on sequence
① Please turn on EN with Vcc≧4.5V or more after impressing Vcc.
② Please fix the potential of DRLIN and THM before turning on EN.
③ A soft start operates at the same time as turning on EN, and the switching is output.
④ After turning on VCC, the order is not related to other input when inputting external PWM from VTH.)
※It leads to the destruction of IC and external parts because it doesn't error output according to an external constant of
adjacent pin 24pin SW terminal, 25pin OUTH terminal, 26pin CS terminal and 27pin BOOT terminal.
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2011.04 - Rev.A