AD7805 查看數據表（PDF） - Analog Devices
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AD7805 Datasheet PDF : 28 Pages
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AD7804/AD7805/AD7808/AD7809
AD7804/AD7805–SPECIFICATIONS (AVDD and DVDD = 3.3 V ؎ 10% to 5 V ؎ 10%; AGND = DGND = 0 V;
Reference = Internal Reference; CL = 100 pF; RL = 2 k⍀ to GND. Sub DAC at Midscale. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
B Grade1
C Grade1
Units
Comments
STATIC PERFORMANCE
MAIN DAC
Resolution
Relative Accuracy
Gain Error
Bias Offset Error2
Zero-Scale Error3
Monotonicity
Minimum Load Resistance
SUB DAC
Resolution
Differential Nonlinearity
10
±3
±3
–80/+40
–VBIAS
16
/ +40
9
2
8
± 0.125
± 0.5
10
±3
±3
–80/+40
–VBIAS
16
/ +40
10
2
8
± 0.125
± 0.5
Bits
LSB max
% FSR max
mV max
mV max
Bits
kΩ min
Bits
LSB typ
LSB max
DAC Code = 0.5 Full Scale
DAC Code = 000H for Offset Binary
and 200H for Twos Complement Coding
Refers to an LSB of the Main DAC
OUTPUT CHARACTERISTICS
Output Voltage Range3
Voltage Output Settling Time to 10 Bits
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DC Output Impedance
Power Supply Rejection Ratio
DAC REFERENCE INPUTS
REF IN Range
REF IN Input Leakage
VBIAS ± 15/16 × VBIAS
VBIAS/16 to 31/16 × VBIAS
4
2.5
1
0.5
0.5
± 0.2
2
0.002
1.0 to VDD/2
±1
VBIAS ± 15/16 × VBIAS
VBIAS/16 to 31/16 × VBIAS
4
2.5
1
0.5
0.5
± 0.2
2
0.002
1.0 to VDD/2
±1
V
V
µs max
V/µs typ
nV-s typ
nV-s typ
nV-s typ
LSB typ
Ω typ
%/% typ
V min to V max
µA max
Twos Complement Coding
Offset Binary Coding
Typically 1.5 µs
1 LSB Change Around the Major Carry
∆VDD ± 10%
Typically ± 1 nA
DIGITAL INPUTS
Input High Voltage, VIH @ VDD = 5 V
Input High Voltage, VIH @ VDD = 3.3 V
Input Low Voltage, VIL @ VDD = 5 V
Input Low Voltage, VIL @ VDD = 3.3 V
Input Leakage Current
Input Capacitance
Input Coding
2.4
2.1
0.8
0.6
± 10
10
Twos Comp/Binary
2.4
2.1
0.8
0.6
µA max
10
Twos Comp/Binary
V min
V min
V max
V max
pF max
REFERENCE OUTPUT
REF OUT Output Voltage
REF OUT Error
REF OUT Temperature Coefficient
REF OUT Output Impedance
1.23
±8
–100
5
1.23
±8
–100
5
V nom
% max
ppm/°C typ
kΩ nom
POWER REQUIREMENTS
VDD (AVDD and DVDD)
IDD (AIDD Plus DIDD)
Normal Mode
System Standby (SSTBY) Mode
Power-Down (PD) Mode
@ +25°C
TMIN–TMAX
Power Dissipation
Normal Mode
System Standby (SSTBY) Mode
Power-Down (PD) Mode
@ +25°C
TMIN–TMAX
3/5.5
12
250
0.8
1.5
66
1.38
4.4
8.25
3/5.5
12
250
0.8
1.5
66
1.38
4.4
8.25
V min to V max
mA max
µA
Excluding Load Currents
VIH = VDD, VIL = DGND
VIH = VDD, VIL = DGND
µA max
µA max
mW max
mW max
VIH = VDD, VIL = DGND
Excluding Power Dissipated in Load
µW max
µW max
NOTES
1Temperature range is – 40°C to +85°C.
2Can be minimized using the Sub DAC.
3VBIAS is the center of the output voltage swing and can be VDD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register.
Specifications subject to change without notice.
–2–
REV. A
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