BR34E02NUX-3R 查看數據表（PDF） - ROHM Semiconductor

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BR34E02NUX-3R

Serial EEPROM Series Standard EEPROM Plug & Play EEPROM

ROHM Semiconductor 

BR34E02-3

Datasheet

Serial Input / Output Timing

tR

tF

tHIGH

SCL

SDA

(IN)

SDA

(OUT)

tHD:STA

tBUF

tSU:DAT tLOW

tPD

tHD:DAT

tDH

SCL

DATA(1)

SDA D1 D0 ACK

WP

tSU：WP

DATA(n)

ACK

tWR

STOP CONDITION

tHD：WP

Figure 1-(a). Serial Input / Output Timing

○SDA data is latched into the chip at the rising edge of SCL clock.

○Output data toggles at the falling edge of SCL clock.

Figure 1-(d). WP Timing of the Write Operation

SCL

tSU:STA

SDA

tHD:STA

tSU:STO

START BIT

Figure 1-(b). Start/Stop Bit Timing

SCL

SDA

DATA(1) D0

D1

ACK

DATA(n)

WP

tHIGH : WP

STOP BIT

ACK

tWR

Figure 1-(e). WP Timing of the Write Cancel Operation

SCL

SDA

D0

WRITE DATA(n)

ACK

tWR

STOP

CONDITION

START

CONDITION

Figure 1-(c). Write Cycle Timing

○For WRITE operation, WP must be "Low" from the rising edge of the

clock (which takes in D0 of first byte) until the end of tWR. (See Figure

1-(d) ) During this period, WRITE operation can be canceled by setting

WP "High".（See Figure 1-(e)）

○When WP is set to "High" during tWR, WRITE operation is immediately

ceased, making the data unreliable. It must then be re-written.

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