BR93LC46-W 查看數據表（PDF） - ROHM Semiconductor
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BR93LC46-W Datasheet PDF : 11 Pages
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Memory ICs
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
zMeasurement circuits
VCC
VCC
VCC
GND
IOL
DO
V VOL
VCC
GND
IOH
DO
V VOH
Control output to "LOW"
Fig.3 "LOW" output voltage circuit
Control output to "HIGH"
Fig.4 "HIGH" output voltage circuit
VIN=0~VCC
VCC
VCC
ILI
A
CS,SK,DI
GND
VCC
VCC
ILO
CS
DO
A
GND
VO=0~VCC
Fig.5 Input leak current circuit
Fig.6 Output leak current circuit
CS
fSK=1MHz / 250kHz / 200kHz
VIN=VIH / VIL
SK
WRITE / READ INPUT
DI
VCC
A ICC
VCC
DO
GND
OPEN
Fig.7 Supply current circuit
Vcc
A ISB
CS
Vcc
SK
DO
OPEN
DI
GND
Fig.8 Standby current circuit
zCircuit operation
(1) Command mode
With these ICs, commands are not recognized or acted upon until the start bit is received. The start bit is taken as
the first “1” that is received after the CS pin rises.
Command
Read (READ) ∗1
Start
bit
1
Operating
code
Address
10 A5~A0
Data
−
Write enabled (WEN)
1
Write (WRITE) ∗2
1
Write all addresses (WRAL) ∗2
1
00 11XXXX
−
01 A5~A0 D15~D0
00 01XXXX D15~D0
Write disabled (WDS)
1
00 00XXXX
−
Erase (ERASE) ∗3
1
11 A5~A0
−
Chip erase (ERAL) ∗3
1
00 10XXXX
−
X: Either VIH or VIL
∗1 After setting of the read command and input of the SK clock, data corresponding to the specified address is output,
with data corresponding to upper addresses then output in se-quence. (Auto increment function)
∗2 When the write or write all addresses command is executed, all data in the selected memory cell is erased
autematically, and the input data is writen to the cell.
∗3 These modes are optinal modes. Please contact Rohm for information on operation timing.
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