BR93LC46-W 查看數據表（PDF） - ROHM Semiconductor
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BR93LC46-W Datasheet PDF : 11 Pages
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Memory ICs
(3) Timing chart
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
CS
tCSS
SK
tDIS
DI
DO (READ)
DO (WRITE)
tSKH
tDIH
tPD0
tSKL
tPD1
STATUS VALID
tCSH
tDF
tDF
· Data is acquired from DI in synchronization with the SK rise.
· During a reading operation, data is output from DO in synchronization with the SK rise.
· During a writing operation, a Status Valid (READY or BUSY) is valid from the time CS is HIGH until time tCS after CS falls following the input of
a write command and before the output of the next command start bit. Also, DO must be in a HIGH-Z state when CS is LOW.
· After the completion of each mode, make sure that CS is set to LOW, to reset the internal circuit, before changing modes.
Fig.9 Synchronized data timing
(4) Reading (Fig.10)
When the read command is acknowledged, the data (16 bits) for the input address is output serially. The data is
synchronized with the SK rise during A0 acquisition and a “0” (dummy bit) is output. All further data is output in
synchronization with the SK pulse rises.
CS
(∗1)
SK
1
2
4
9 10
25 26
DI
1
1
0 A5 A4
DO
High Z
A1 A0
0 D15 D14
(∗2)
D1 D0 D15 D14
∗( 1) If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in succession, the
"1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently.
∗( 2) Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations. With
this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession.
CS is held in HIGH state during automatic incrementing.
Fig.10 Read cycle timing (READ)
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