BR93LC46-W 查看數據表（PDF） - ROHM Semiconductor
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BR93LC46-W Datasheet PDF : 11 Pages
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Memory ICs
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
(5) Write enable (Fig.11)
These ICs are set to the write disabled state by the internal reset circuit when the power is turned on. Therefore,
before performing a write command, the write enable command must be executed. When this command is
executed, it remains valid until a write disable command is issued or the power supply is cut off. However, read
commands can be used in either the write enable or write disable state.
CS
SK
DI
1
0
0
1
1
DO
High Z
Fig.11 Write enable cycle timing
(6) Write (Fig.12)
This command writes the input 16 bits data (D15 to D0) to the specified address (A5 to A0). Actual writing of the data
begins after CS falls (following the 25th clock pulse after the start bit input), and D0 is in the Acquire state.
STATUS is not detected if CS = LOW after the time tE / W. When STATUS is detected (CS = HIGH), no commands are
accepted while DO is LOW (BUSY). Therefore, no commands should be input during this period.
CS
1
2
4
SK
9
10
tCS
STATUS
25
DI
1
DO
High Z
0
1
A5 A4
A1 A0 D15 D14
Fig.12 Write cycle timing (WRITE)
D1 D0
tSV
BUSY READY
tE / W
(STATUS)
After time tCS following the fall of CS, after input of the write command), if CS is set to HIGH, the write execute = BUSY
(LOW) and the command wait status READY (HIGH) are output.
If in the command wait status (STATUS = READY), the next command can be performed within the time tE / W. Thus, if
data is input via SK and DI with CS = HIGH in the tE / W period, erroneous operations may be performed. To avoid this,
make sure that DI = LOW when CS = HIGH. (Caution is especially important when common input ports are used.) This
applies to all of the write commands.
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