BS616LV8016 查看數據表（PDF） - Brilliance Semiconductor

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BS616LV8016

Very Low Power CMOS SRAM 512K X 16 bit

Brilliance Semiconductor 

n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)

SYMBOL

PARAMETER

TEST CONDITIONS

VDR

ICCDR(3)

tCDR

tR

VCC for Data Retention

Data Retention Current

Chip Deselect to Data

Retention Time

Operation Recovery Time

CE1≧VCC-0.2V or CE2≦0.2V,

VIN≧VCC-0.2V or VIN≦0.2V

CE1≧VCC-0.2V or CE2≦0.2V,

VIN≧VCC-0.2V or VIN≦0.2V

See Retention Waveform

1. VCC=1.5V, TA=25OC and not 100% tested.

2. tRC = Read Cycle Time.

3. ICCDR(Max.) is 2.0uA at TA=70OC.

n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)

VCC

CE1

VCC

tCDR

VIH

Data Retention Mode

VDR≧1.5V

CE1≧VCC - 0.2V

n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)

VCC

VCC

tCDR

Data Retention Mode

VDR≧1.5V

CE2

CE2≦0.2V

VIL

BS616LV8016

MIN. TYP. (1) MAX. UNITS

1.5

--

--

V

--

0.4

4.0

uA

0

--

tRC (2)

--

--

ns

--

ns

VCC

tR

VIH

VCC

tR

VIL

n AC TEST CONDITIONS

(Test Load and Input/Output Reference)

n KEY TO SWITCHING WAVEFORMS

Input Pulse Levels

Vcc / 0V

Input Rise and Fall Times

Input and Output Timing

Reference Level

Output Load

tCLZ, tOLZ, tCHZ, tOHZ, tWHZ

Others

1V/ns

0.5Vcc

CL = 5pF+1TTL

CL = 30pF+1TTL

Output

1 TTL

CL(1)

VCC

GND

ALL INPUT PULSES

90%

10%

→←

Rise Time:

1V/ns

90%

10%

→←

Fall Time:

1V/ns

1. Including jig and scope capacitance.

WAVEFORM INPUTS

OUTPUTS

MUST BE

STEADY

MAY CHANGE

FROM “H” TO “L”

MAY CHANGE

FROM “L” TO “H”

DON’T CARE

ANY CHANGE

PERMITTED

DOES NOT

APPLY

MUST BE

STEADY

WILL BE CHANGE

FROM “H” TO “L”

WILL BE CHANGE

FROM “L” TO “H”

CHANGE :

STATE UNKNOW

CENTER LINE IS

HIGH INPEDANCE

“OFF” STATE

R0201-BS616LV8016

4

Revision 2.3

May.

2006

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