BS616LV8016 查看數據表（PDF） - Brilliance Semiconductor

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BS616LV8016

Very Low Power CMOS SRAM 512K X 16 bit

Brilliance Semiconductor 

READ CYCLE 2 (1,3,4)

CE1

CE2

DOUT

READ CYCLE 3 (1, 4)

ADDRESS

OE

CE1

CE2

LB, UB

DOUT

tACS1

tACS2

tCLZ(5)

tRC

tAA

tOE

tOLZ

tCLZ1(5)tACS1

t tCLZ2(5) ACS2

tBA

tBE

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = VIL and CE2= VIH.

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = VIL.

5. Transition is measured ± 500mV from steady state with CL = 5pF.

The parameter is guaranteed but not 100% tested.

BS616LV8016

tCHZ(5)

tOH

tOHZ(5)

tCHZ(1,5)

tCHZ2(2,5)

tBDO

R0201-BS616LV8016

6

Revision 2.3

May.

2006

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