SAA7201H 查看數據表（PDF） - Philips Electronics

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SAA7201H

3.3 V, integrated MPEG2 AVG decoder / QFP160 Package

Philips Electronics 

Philips Semiconductors

Integrated MPEG2 AVG decoder

Objective specification

SAA7201

FEATURES

General

• Uses single external Synchronous DRAM (SDRAM)

organized as 1M × 16 interfacing at 81 MHz; compatible

with the SDRAM ‘lite’ or ‘PC’

• Fast external CPU interface; 16-bit data + 8-bit address

• Dedicated input for audio and video data in PES or ES

format; data input rate: ≤9 Mbytes/s in byte mode;

≤20 Mbit/s in bit serial mode; audio and/or video data

can also serve as input via CPU interface

• Single 27 MHz external clock for time base reference

and internal processing; all required decoding and

presentation clocks are generated internally

• Internal system time base at 90 kHz can be

synchronized via CPU port

• Flexible memory allocation under control of the external

CPU enables optimized partitioning of memory for

different tasks

• Boundary scan (JTAG) plus external SDRAM self test

implemented

• Supply voltage 3.3 V

• Package 160 QFP.

CPU relation

• 16-bit data, 8-bit address, or 16-bit multiplexed bus;

Motorola and Intel mode supported

• Support for fast DMA transfer to either internal registers

or external SDRAM

• Maximum sustained rate to the external SDRAM is

9 Mbytes/s.

MPEG2 system

• Parsing of MPEG2 PES and MPEG1 packet streams

• Double System Time Clock (STC) counters for

discontinuity handling

• Time stamps or CPU controlled audio/video

synchronization

• Support for seamless time base change (edition)

• Processing of errors flagged by channel decoding or

demux section

• Support for retrieval of PES header and PES private

data.

MPEG2 audio

• Decoding of 2 channel, layer I and II MPEG audio;

support for mono, stereo, intensity stereo and dual

channel mode

• Constant and variable bit rates up to 448 kbit/s

• Audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and

16 kHz

• CRC error detection

• Selectable output channel in dual channel mode

• Independent volume control for both channels and

programmable inter-channel crosstalk control through a

baseband audio processing unit

• Storage ancillary data up to 54 bytes

• Dynamic range control at output

• Muting possibility via external controller; automatic

muting in case of errors

• Generation of ‘beeps’ with programmable tone height,

duration and amplitude

• Serial two channel digital audio output with 16, 18, 20 or

22 bits per sample, compatible with either I2S or

Japanese formats

• Serial SPDIF audio output

• Clock output 256 or 384 × fs for external D/A converter

• Audio input buffer in external SDRAM with

programmable size (default is 64 kbit)

• Programmable processing delay compensation

• Software controlled stop, pause, restricted skip, and

restart functions.

MPEG2 video

• Decoding of MPEG2 video up to main level, main profile

• Nominal video input buffer size equals 2.6 Mbit for Video

Main Profile and Main Level (MP@ML)

• Output picture format: CCIR-601 4 : 2 : 2 interlaced

pictures; picture format 720 × 576 at 50 Hz or 720 × 480

at 60 Hz

• 3 : 2 pull-down supported with 24 and 30 Hz sequences

• Support of constant and variable bit rates up to 15 Mbit/s

• Output interface at 8-bit wide, 27 MHz UYVY

multiplexed bus

• Horizontal and vertical pan and scan allows the

extraction of a window from the coded picture

1997 Jan 29

2

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