SAA7201H/B/C2 查看數據表（PDF） - Philips Electronics
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SAA7201H/B/C2 Datasheet PDF : 36 Pages
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Philips Semiconductors
Integrated MPEG2 AVG decoder
BLOCK DIAGRAM
Objective specification
SAA7201
handbook, full pagewidth
VDDCO1 to
SDRAM_WE
SDRAM_DATA
READI
VDDA
VDDCO4 SDRAM_CAS SDRAM_UDQ (15 to 0) CP81MEXT
SDRAM_RAS
SDRAM_ADDR
(11 to 0)
CP81M READO
VDD1 to
VDD16
77 75 74 78
16 84 83 81 80
121
4
12
16
MEMORY
INTERFACE
A_STROBE 159
V_STROBE 148
8
AV_DATA(0 to 7)
ERROR 147
AUDIO/VIDEO
INTERFACE
CPU_TYPE
MUX
CS
DS
AS
R/W
DTACK
ADDRESS(8 to 1)
DATA(15 to 0)
IRQ(3 to 0)
DMA_REQ
DMA_ACK
DMA_RDY
DMA_DONE
CLK
RESET
2
1
8
9
10
11
12
8
16
4
4
3
6
5
124
138
SYSTEM TIME
BASE UNIT
HOST
INTERFACE
CLOCK
GENERATION
SAA7201
VIDEO INPUT
BUFFER & SYNC
VIDEO
DECODER
DISPLAY
UNIT
106
HS
107
VS
GRAPHICS
UNIT
AUDIO
DECODER
8
119
143
142
145
146
139
YUV(7 to 0)
GRPH
SD
SCLK
WS
SPDIF
FSCLK
JTAG
4
16
VSSCO1 to VSSCO4 VSS1 to VSS16
AUDIO INPUT
BUFFER & SYNC
122
VSSA
MGD322
1997 Jan 29
Fig.1 Block diagram.
5
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