SAA7201H/C1/S1 查看數據表（PDF） - Philips Electronics
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SAA7201H/C1/S1 Datasheet PDF : 36 Pages
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Philips Semiconductors
Integrated MPEG2 AVG decoder
PINNING
SYMBOL
MUX
CPU_TYPE
DMA_ACK
DMA_REQ
DMA_DONE
DMA_RDY
VSS1
CS
DS
AS
R/W
DTACK
VDD1
IRQ0
IRQ1
IRQ2
IRQ3
VSS2
VSSCO1
VDDCO1
DATA0
DATA1
DATA2
DATA3
VDD2
DATA4
DATA5
DATA6
DATA7
VSS3
DATA8
DATA9
DATA10
DATA11
VDD3
DATA12
DATA13
DATA14
DATA15
VSS4
1997 Jan 29
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DESCRIPTION
multiplexed/non-multiplexed (active LOW) bus input
Intel/Motorola (active LOW) selection input
DMA acknowledge input
DMA request input and output
DMA end input
DMA ready output
ground for pad ring
chip select input
data strobe input
address strobe input
read/write (active LOW) input
data acknowledge output
supply for pad ring
individually maskable interrupts
individually maskable interrupts
individually maskable interrupts
individually maskable interrupts
ground for pad ring
ground for core logic
supply for core logic
CPU data interface
CPU data interface
CPU data interface
CPU data interface
supply for pad ring
CPU data interface
CPU data interface
CPU data interface
CPU data interface
ground for pad ring
CPU data interface
CPU data interface
CPU data interface
CPU data interface
supply for pad ring
CPU data interface
CPU data interface
CPU data interface
CPU data interface
ground for pad ring
6
Objective specification
SAA7201
V
I/O
5.0 I
5.0 I
3.3 I
3.3 I/O
3.3 I
3.3 O/Z
3.3 −
5.0 I
5.0 I
5.0 I
5.0 I
5.0 O/Z
3.3 −
3.3 O/Z
3.3 O/Z
3.3 O/Z
3.3 O/Z
−
−
−
−
3.3 −
5.0 I/O
5.0 I/O
5.0 I/O
5.0 I/O
3.3 −
5.0 I/O
5.0 I/O
5.0 I/O
5.0 I/O
−
−
5.0 I/O
5.0 I/O
5.0 I/O
5.0 I/O
−
−
5.0 I/O
5.0 I/O
5.0 I/O
5.0 I/O
−
−
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