SAA7201H/A/C2 查看數據表（PDF） - Philips Electronics
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SAA7201H/A/C2 Datasheet PDF : 36 Pages
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Philips Semiconductors
Integrated MPEG2 AVG decoder
SYMBOL
PIN
READO
81
VSS9
82
CP81MEXT
83
CP81M
84
VDD9
85
SDRAM_ADDR8 86
SDRAM_ADDR9 87
SDRAM_ADDR11 88
VSS10
89
SDRAM_ADDR7 90
SDRAM_ADDR10 91
SDRAM_ADDR6 92
VDD10
93
SDRAM_ADDR0 94
SDRAM_ADDR5 95
SDRAM_ADDR1 96
VSS11
97
SDRAM_ADDR4 98
SDRAM_ADDR2 99
SDRAM_ADDR3 100
VSSCO3
101
VDDCO3
102
VDD11
103
TEST8
104
TEST7
105
HS
106
VS
107
VSS12
108
YUV0
109
YUV1
110
YUV2
111
YUV3
112
VDD12
113
YUV4
114
YUV5
115
YUV6
116
YUV7
117
TEST6
118
GRPH
119
TEST5
120
DESCRIPTION
read command output
ground for pad ring
81 MHz clock return path input
81 MHz memory clock output
supply for pad ring
memory address
memory address
memory address
ground for pad ring
memory address
memory address
memory address
supply for pad ring
memory address
memory address
memory address
ground for pad ring
memory address
memory address
memory address
ground for core logic
supply for core logic
supply for pad ring
IC test interface
IC test interface
horizontal synchronization input and output
vertical synchronization input and output
ground for pad ring
YUV video output at 27 MHz
YUV video output at 27 MHz
YUV video output at 27 MHz
YUV video output at 27 MHz
supply for pad ring
YUV video output at 27 MHz
YUV video output at 27 MHz
YUV video output at 27 MHz
YUV video output at 27 MHz
IC test interface
indicator for graphics information output
IC test interface
1997 Jan 29
8
Objective specification
SAA7201
V
I/O
3.3 O
−
−
3.3 I
3.3 O
3.3 −
3.3 O
3.3 O
3.3 O
−
−
3.3 O
3.3 O
3.3 O
3.3 −
3.3 O
3.3 O
3.3 O
−
−
3.3 O
3.3 O
3.3 O
−
−
3.3 −
3.3 −
3.3 I/O
3.3 I/O
3.3 I/O
3.3 I/O
−
−
3.3 O/Z
3.3 O/Z
3.3 O/Z
3.3 O/Z
3.3 −
3.3 O/Z
3.3 O/Z
3.3 O/Z
3.3 O/Z
3.3 I/O
3.3 O
3.3 I/O
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