BT817AKTF 查看數據表（PDF） - Unspecified

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BT817AKTF

VideoStream™ Decoders

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FUNCTIONAL DESCRIPTION

Pin Descriptions

Bt819A/7A/5A

Table 2. Pin Descriptions Grouped By Pin Function (3 of 6)

Pin # I/O Pin Name

Description

The Video Timing Unit Pins

82

O HRESET

Horizontal Reset Output (TTL Compatible). This signal indicates the beginning of a

new line of video.

In SPI mode: this signal is 64 CLKx1 clock cycles wide. In SPI mode, the falling

edge of this output indicates the beginning of a new scan line of video.

In API mode: this signal is one clock cycle wide and is output relative to CLKIN.

In API mode, it immediately follows the last active pixel of a line.

Note: The polarity of this pin is programmable through the VPOLE register.

79

O VRESET

Vertical Reset Output (TTL Compatible). This signal indicates the beginning of a

new field of video.

In SPI mode: this signal is output coincident with the rising edge of CLKx1, and

is normally six lines wide. The falling edge of VRESET indicates the beginning of a

new field of video.

In API mode: this signal is a one clock cycle wide, active low pulse output rela-

tive to CLKIN. It immediately follows the HRESET pixel, and it indicates that the

next active pixel is the first active pixel of the next field.

Note: The polarity of this pin is programmable through the VPOLE register.

83

O ACTIVE

Active Video output (TTL compatible). This pin is a logical high during the

active/viewable periods of the video stream. The active region of the video stream

is programmable.

Note: The polarity of this pin is programmable through the VPOLE register.

85

I

RDEN

Asynchronous FIFO Read Enable signal (TTL compatible). A logical high on this

pin enables a read from the output FIFO. When using the Bt819A in SPI mode,

RDEN must be pulled low.

G GND

Ground for digital circuitry on Bt817A and Bt815A.

94

O QCLK

98

I

OE

Qualified Clock Output. See “Output Interface” on page 37 for a complete descrip-

tion of the QCLK pin functions.

Output Enable control (TTL compatible). All video timing unit output pins and all

clock interface output pins contain valid data following the rising edge of CLKIN,

after OE has been asserted low. The above outputs are three-stated when OE is

held high. This function is asynchronous. The three-stated pins include: VD[15:0],

HRESET, VRESET, ACTIVE, DVALID, CBFLAG, FIELD, AEF, AFF, QCLK, CLKx1,

and CLKx2.

78

O FIELD

Odd/even field output (TTL compatible). High state on FIELD pin indicates that an

even field is being digitized.

Note: The polarity of this pin is programmable through the VPOLE register.

89

O CBFLAG

Cb data identifier (TTL compatible). High state on this pin indicates that VD[7:0]

bus contains Cb chroma information.

Note: The polarity of this pin is programmable through the VPOLE register.

8

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