BT817AKTF 查看數據表（PDF） - Unspecified

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BT817AKTF

VideoStream™ Decoders

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FUNCTIONAL DESCRIPTION

Pin Descriptions

Bt819A/7A/5A

Table 2. Pin Descriptions Grouped By Pin Function (5 of 6)

Pin # I/O Pin Name

Description

The Clock Interface Pins

12

A XT0I

13

A XT0O

Clock Zero pins. A 28.64 MHz (8*Fsc) fundamental (or third harmonic) crystal can

be tied directly to these pins, or a single-ended oscillator can be connected to XT0I.

CMOS level inputs must be used. This clock source is selected for NTSC input

sources. When the chip is configured to decode PAL but not NTSC (and therefore

only one clock source is needed), the 35.47 MHz source is connected to this port

(XT0).

16

A XT1I

17

A XT1O

Clock One pins. A 35.47 MHz (8*Fsc) fundamental (or third harmonic) crystal can

be tied directly to these pins, or a single-ended oscillator can be connected to XT1I.

CMOS level inputs must be used. This clock source is selected for PAL input

sources. If either NTSC or PAL is being decoded, and therefore only XT0I and

XT0O are connected to a crystal, XT1I should be tied either high or low, and XT1O

must be left floating.

97

O CLKX1

99

O CLKX2

1x clock output (TTL compatible). The frequency of this clock is 4*Fsc (14.31818

MHz for NTSC or 17.734475 MHz for PAL).

2x clock output (TTL compatible). The frequency of this clock is 8*Fsc (28.63636

MHz for NTSC, or 35.46895 MHz for PAL).

80

I

NUMXTAL

Crystal Format Pin. This pin is set to indicate whether one or two crystals are

present so that the Bt819A can select XT1 or XT0 as the default in auto format

mode. A logical zero on this pin indicates one crystal is present. A logical one indi-

cates two crystals are present. This pin is internally pulled down to ground with an

effective 18 KΩ resistance.

The JTAG Pins

34

I

TCK

Test clock (TTL compatible). Used to synchronize all JTAG test structures. When

JTAG operations are not being performed, this pin must be driven to a logical low.

36

I

TMS

Test Mode Select (TTL compatible). JTAG input pin whose transitions drive the

JTAG state machine through it sequences. When JTAG operations are not being

performed, this pin must be left floating or tied high.

37

I

TDI

Test Data Input (TTL compatible). JTAG pin used for loading instruction to the TAP

controller or for loading test vector data for boundary-scan operation. When JTAG

operations are not being performed, this pin must be left floating or tied high.

32

O TDO

Test Data Output (TTL compatible). JTAG pin used for verifying test results of all

JTAG sampling operations. This output pin is active for certain JTAG operations

and will be three-stated at all other times.

35

I

TRST

Test Reset (TTL compatible). JTAG pin used to initialize the JTAG controller. This

pin is tied low for normal device operation. When pulled high, the JTAG controller is

ready for device testing.

10

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