AS7C33128PFS36A-150TQI 查看數據表（PDF） - Alliance Semiconductor

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AS7C33128PFS36A-150TQI

3.3V 128K X 32/36 pipeline burst synchronous SRAM

Alliance Semiconductor 

7C33128PFS32A

7C33128PFS36A

®

Timing characteristics over operating range

Parameter

Symbo –166

–150

–133

–100

Notes

l Min Max Min Max Min Max Min Max Unit *

Clock frequency

Cycle time (pipelined mode)

Cycle time (flow-through mode)

Clock access time (pipelined mode)

Clock access time (flow-through

mode)

fMax – 166 – 150 – 133 – 100 MHz

tCYC

6

– 6.6 – 7.5 – 10 –

ns

tCYCF 10 – 10 – 12 – 12 – ns

tCD – 3.5 – 3.8 – 4.0 – 5.0 ns

tCDF

–

9

– 10 – 10 – 12 ns

Output enable LOW to data valid

tOE – 3.5 – 3.8 – 4.0 – 5.0 ns

Clock HIGH to output Low Z

tLZC 0 – 0 – 0 – 0 – ns 2,3,4

Data output invalid from clock HIGH tOH 1.5 – 1.5 – 1.5 – 1.5 – ns

2

Output enable LOW to output Low Z tLZOE 0 – 0 – 0 – 0 – ns 2,3,4

Output enable HIGH to output High Z tHZOE – 3.5 – 3.8 – 4.0 – 4.5 ns 2,3,4

Clock HIGH to output High Z

tHZC – 3.5 – 3.8 – 4.0 – 5.0 ns 2,3,4

Output enable HIGH to invalid output tOHOE 0 – 0 – 0 – 0 – ns

Clock HIGH pulse width

tCH 2.4 – 2.5 – 2.5 – 3.5 – ns

5

Clock LOW pulse width

tCL 2.4 – 2.5 – 2.5 – 3.5 – ns

5

Address setup to clock HIGH

tAS 1.5 – 1.5 – 1.5 – 2.0 – ns

6

Data setup to clock HIGH

tDS 1.5 – 1.5 – 1.5 – 2.0 – ns

6

Write setup to clock HIGH

tWS 1.5 – 1.5 – 1.5 – 2.0 – ns 6,7

Chip select setup to clock HIGH

tCSS 1.5 – 1.5 – 1.5 – 2.0 – ns 6,8

Address hold from clock HIGH

tAH 0.5 – 0.5 – 0.5 – 0.5 – ns

6

Data hold from clock HIGH

tDH 0.5 – 0.5 – 0.5 – 0.5 – ns

6

Write hold from clock HIGH

tWH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,7

Chip select hold from clock HIGH

tCSH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,8

ADV setup to clock HIGH

tADVS 1.5 – 1.5 – 1.5 – 2.0 – ns

6

ADSP setup to clock HIGH

tADSPS 1.5 – 1.5 – 1.5 – 2.0 – ns

6

ADSC setup to clock HIGH

tADSCS 1.5 – 1.5 – 1.5 – 2.0 – ns

6

ADV hold from clock HIGH

tADVH 0.5 – 0.5 – 0.5 – 0.5 – ns

6

ADSP hold fromclock HIGH

tADSPH 0.5 – 0.5 – 0.5 – 0.5 – ns

6

ADSC hold from clock HIGH

tADSCH 0.5 – 0.5 – 0.5 – 0.5 – ns

6

*See “Notes” on page 10.

Key to switching waveforms

Rising input

Falling input

Undefined/don’t care

2/1/01

Alliance Semiconductor

P. 6 of 11

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