AS7C1025A-15HFC 查看數據表（PDF） - Alliance Semiconductor
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AS7C1025A-15HFC Datasheet PDF : 8 Pages
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AS7C1025A
AS7C31025A
®
Write waveform 2 (CE controlled)
tWC
tAW
Address
CE
WE
DIN
DOUT
tAS
tCW
tWP
tWZ
tDW
Data valid
tAH
tWR
tDH
AC test conditions
– Output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
+5V
+3.0V
90%
90%
10%
GND
2 ns
10%
Figure A: Input pulse
DOUT
255Ω
480Ω
C(14)
GND
Figure B: 5V Output load
Thevenin equivalent:
168Ω
DOUT
+1.728V (5V and 3.3V)
+3.3V
DOUT
255Ω
320Ω
C(14)
GND
Figure C: 3.3V Output load
Notes
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4 tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6 WE is High for read cycle.
7 CE and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 NA.
13 C=30pF, except all high Z and low Z parameters, where C=5pF.
5/28/03; v.0.9.9
Alliance Semiconductor
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