V436516R04VATG-10PC 查看數據表（PDF） - Mosel Vitelic Corporation

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V436516R04VATG-10PC

3.3 VOLT 16M x 64 (using 8M x 16) PC100 UNBUFFERED SDRAM MODULE

Mosel Vitelic Corporation  

MOSEL VITELIC

.

tCH

CLOCK

tCL

tSETUP tHOLD

2.4V

0.4V

tT

INPUT

1.4V

V436516R04VATG-10PC

+ 1.4 V

50 Ohm

Z=50 Ohm

I/O

50 pF

OUTPUT

tAC

tLZ

tAC

tOH

tHZ

1.4V

I/O

50 pF

Measurement conditions for

tac and toh

5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.

6. Rated at 1.5V

7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter.

8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be

given to “wake-up” the device.

9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.

Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command

is registered.

10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.

11. tDAL is equivalent to tDPL + tRP.

V436516R04VATG-10PC Rev. 1.1 February 2001

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