AS7C3256PFS16A-4TQC 查看數據表（PDF） - Alliance Semiconductor
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AS7C3256PFS16A-4TQC Datasheet PDF : 11 Pages
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AS7C3256PFS16A
AS7C3256PFS18A
Advance information
®
1 This parameter is guaranteed but not tested.
2 For test conditions, see AC Test Conditions, Figures A, B, C.
6 ICC given with no output loading. I CC increases with faster cycle times
and greater output loading.
3 This parameter is sampled and not 100% tested.
7 Transitions are measured ±500 mV from steady state voltage. Output
4 This is a synchronous device. All addresses must meet the specified setup
loading specified with CL = 5 pF as in Figure C.
and hold times for all rising edges of CLK. All other synchronous inputs 8 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature
must meet the setup and hold times with stable logic levels for all rising
and voltage.
edges of CLK when chip is enabled.
5 Typical values measured at 3.3V, 25°C and 10 ns cycle time.
9 tHZCN is a‘no load’ parameter to indicate exactly when SRAM outputs
have stopped driving.
• Output Load: see Figure B,
except for tLZC, tLZOE, tHZOE, tHZC see Figure C.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.0V
90%
10%
GND
90%
10%
Z0=50Ω
50Ω
Dout
VL=1.5V
30 pF*
Figure A: Input waveform
Figure B: Output load (A)
+3.3V
Dout
351Ω
317Ω
5 pF*
GND *including scope
and jig capacitance
Figure C: Output load(B)
Package
TQFP
TQFP
Width
×16
×18
166 MHz
AS7C3256PFS16A-3.5TQC
AS7C3256PFS18A-3.5TQC
150 MHz
AS7C3256PFS16A-3.8TQC
AS7C3256PFS18A-3.8TQC
133 MHz
AS7C3256PFS16A-4TQC
AS7C3256PFS18A-4TQC
100 MHz
AS7C3256PFS16A-5TQC
AS7C3256PFS18A-5TQC
AS7C 3
256K36
SRAM Operating Part number,
prefix voltage organization
P
S
16, 18
Timing
S = Single-
P=PBSRAM cycle deselect Organization
–XX
Access
time (ns)
XX
C
Package: Commercial temperature,
TQ = TQFP 0°C to 70 °C
11
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DID 11-20027-A. 6/8/00
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