AS7C3256PFS16A 查看數據表（PDF） - Alliance Semiconductor
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AS7C3256PFS16A Datasheet PDF : 11 Pages
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AS7C3256PFS16A
AS7C3256PFS18A
Advance information
®
The AS7C3256PFS16A and AS7C3256PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 262,144 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC-based systems in computing, datacomm, instrumentation, and telecommunications systems.
Fast cycle times of 6/6.7/7.5/10 ns with clock access times (tCD) of 3.5/3.5/3.8/5.0 ns enable 167, 150, 133 and 100 MHz bus
frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the control ler address
strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when WE is sampled HIGH, ADV is sampled LOW,
and both address strobes are HIGH. Burst operation is selectable with the MODE input. With MODE unconnected or driven HIGH, burst
operations use a Pentium count sequence. With MODE driven LOW the device uses a linear count sequence, suitable for PowerPC and many
other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
32 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BW signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst of address if BWn and ADV are sampled LOW.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C3256PFS16A and AS7C3256PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or .3V.
These devices are available in a 100-pin 14×20 mm TQFP packaging.
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
CI/O
Signals
Address and control pins
I/O pins
Test conditions
Vin = 0V
Vin = Vout = 0V
Max
Unit
4
pF
5
pF
GWE
L
H
H
H
Key: X = Don’t Care, L = LOW, H = HIGH
BWE
X
L
H
L
BWn
Function
X
Write all Bytes
L
Write Byte(s)n
X
Read
H
Read
2
ALLIANCE SEMICONDUCTOR
DID 11-20027-A. 6/8/00
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