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BU7262SF 查看數據表(PDF) - ROHM Semiconductor

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BU7262SF Datasheet PDF : 37 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
BU7261/BU7261S family, BU7241/BU7241S family, BU7295/BU7295S family, BU7275/BU7275S family
BU7262/BU7262S family, BU7242/BU7242S family, BU7264/BU7264S family, BU7244/BU7244S family Technical Note
BU7242 family (Unless otherwise specified VDD=+3[V], VSS=0[V], Ta=25[])
Limits
Parameter
Symbol
Temperature
Range
BU7242F/FVM/NUX
BU7242S F/FVM/NUX
Min. Typ. Max.
Input Offset Voltage (*17) (*18)
25
1
9
Vio
Full range
10
Input Offset Current (*17)
Iio
25
1
Unit
Condition
mV
VDD=1.8 ~ 5.5[V]
VOUT=VDD/2
pA
Input Bias Current (*17)
Supply Current (*18)
High Level Output Voltage
Ib
25
1
IDD
25
180
Full range
VOH
25VDD-0.1
pA
360
600
μA
RL=All Op-Amps
AV=0[dB], VIN=1.5[V]
V RL=10[k]
Low Level Output Voltage
VOL
25
VSS+0.1 V RL=10[k]
Large Signal Voltage Gain
AV
25
70
95
dB RL=10[k]
Input Common-mode Voltage Range Vicm
25
0
3
V VDD-VSS=3[V]
Common-mode Rejection Ratio
CMRR 25
45
60
dB
Power Supply Rejection Ratio
Output Source Current (*19)
Output Sink Current (*19)
PSRR
IOH
IOL
25
25
25
60
80
dB
4
10
mA VDD-0.4[V]
5
12
mA VSS+0.4[V]
Slew Rate
SR
25
0.4
V/μs CL=25[pF]
Gain Band width
FT
25
0.9
MHz CL=25[pF], AV=40[dB]
Phase Margin
θ
25
50
° CL=25[pF], AV=40[dB]
Total Harmonic Distortion
THD
25
0.05
%
VOUT=0.8[Vp-p],
f=1[kHz]
Channel Separation
CS
25
100
dB AV=40[dB]
(*17) Absolute value
(*18) Full range: BU7242: Ta=-40[] ~ +85[] BU7242S: Ta=-40[] ~ +105[]
(*19) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
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2010.12 - Rev.A

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