V436532Z04VATG-10PC 查看數據表（PDF） - Mosel Vitelic Corporation

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V436532Z04VATG-10PC

3.3 VOLT 32M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE

Mosel Vitelic Corporation  

MOSEL VITELIC

SPD-Table: (Continued)

Byte

Number Function Described

30

Minimum RAS Pulse Width tRAS

31

Module Bank Density (Per Bank)

32

SDRAM Input Setup Time

33

SDRAM Input Hold Time

34

SDRAM Data Input Setup Time

35

SDRAM Data Input Hold Time

36-61 Superset Information (May be used in Future)

62

SPD Revision

63

Checksum for Bytes 0 - 62

64-125

Manufacturers’s Information (Optional)

(FFh if not used)

126

Max. Frequency Specification

127

100 MHz Support Details

128+ Unused Storage Location

DC Characteristics

TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V

Symbol Parameter

VIH

Input High Voltage

VIL

Input Low Voltage

VOH

Output High Voltage (IOUT = –2.0 mA)

VOL

Output Low Voltage (IOUT = 2.0 mA)

II(L)

Input Leakage Current, any input

(0 V < VIN < 3.6 V, all other inputs = 0V)

IO(L)

Output leakage current

(DQ is disabled, 0V < VOUT < VCC)

V436532S04VATG-10PC

SPD Entry Value

45 ns

128 MByte

2 ns

1 ns

2 ns

1 ns

Revision 1.2

100 MHz

Hex Value

100 MHz

-10PC

2D

20

20

10

20

10

00

12

FD

64

FF

00

Limit Values

Min.

Max.

2.0

–0.5

V CC +0.3

0.8

2.4

—

—

0.4

–40

40

–40

40

Unit

V

V

V

V

µA

µA

V436532S04VATG-10PC Rev. 1.0 February 2001

5

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