AS4LC8M8S0-75TC 查看數據表（PDF） - Alliance Semiconductor
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AS4LC8M8S0-75TC Datasheet PDF : 24 Pages
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AS4LC4M16S0
AS4LC16M4S0
®
Commands
Command
Register Mode register set
BA0/
CKEn-1 CKEn CS RAS CAS WE DQM BA1 A10 A9–A0
H* H L L L L X
Op code
DQ Note
X 1,2
Auto refresh
H HLL LH X –
–
3
Refresh Self
Entry
refresh Exit
H L LL LH X –
–
X
LHHH X –
–
LH
HX X X X –
–
3
X
3
3
Bank activate
H H L L H H X V row address X
Read
Auto precharge disable
H
Auto precharge enable
H LH L H X
V
L column
H address
X
4
4,5
Auto precharge disable
Write
H
Auto precharge enable
H LH L L
X
V
L
H
column
address
Valid
4
4,5
Burst stop
H H LHH L X
X
Active 6
Selected bank
Precharge
All banks
VL
H HLLHL X
X
XH
X4
Clock suspend or Entry
active power down
Exit
HX X X
HL
LV V V X
XX
X
X
L HXX X X
Precharge power
down mode
Entry
Exit
HX X X
HL
LH H H
X
XX
X
X
HX X X
LH
LV V V
Write enable/output
enable
XX X X
XX
X
DQM
HH
H
Write inhibit/Output
High-Z
X7
No operation command
HX X X X
HX
XX
X
X
LHHH X
1 OP = operation code.
A0~A11 and BA0~BA1 program keys.
2 MRS can be issued only when all banks are precharged. A new command can be issued 1 clock cycle after MRS.
3 Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.
Auto/self refresh can only be issued after all banks are precharged.
4 BA0~BA1: bank select addresses.
If A10/AP is High at row precharge, BA0 and BA1 are ignored and all banks are selected.
During read, write, row active, and prechage:
If BA0 and BA1 are Low, Bank A is selected.
If BA0 = Low and BA1 = High, Bank B is selected.
If BA0 = High and BA1 = Low, Bank C is selected.
If BA0 and BA1 are High, Bank D is selected.
5 A new read/write command to the same bank cannot be issued during a burst read/write with auto precharge.
A new row active command can be issued after t(t RP/tCK + BL +) cycles.
6 Burst stop command valid at every burst length.
7 DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
4
ALLIANCE SEMICONDUCTOR
7/5/00
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