AS4LC8M8S0-75TC 查看數據表（PDF） - Alliance Semiconductor

零件编号

产品描述 (功能)

生产厂家

AS4LC8M8S0-75TC

3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

Alliance Semiconductor 

AS4LC8M8S0

AS4LC4M16S0

®

IDD specifications and conditions

(0° C ≤ TA ≤ 70° C, VDD, VDDQ = +3.3V ± 0.3V)

Max

Parameter

Symbol –75

–8 –10F/10 Units

Operating current: active mode; burst = 2; READ or WRITE;

tRC = tRC(min); CAS latency = 3

IDD1

Standby current: power-down mode; all banks idle;

CKE = low

IDD2

115

95

2

2

95

mA

2

mA

Standby current: active mode; CKE = high; CS# = high; all

banks active after tRCD met; no accesses in progress

IDD3

Operating current: burst mode; continuous burst; READ or

WRITE; all banks active; CAS latency = 3

IDD4

45

35

35

mA

140

130

120 mA

Auto refresh current: CKE = high;

tRFC = tRFC(min);

CL = 3

IDD5

210

210

190 mA

CS# = high

tRFC = 15.625ms;

CL = 3

IDD6

50

50

40

mA

Self-refresh current: CKE ≤ 0.2V

IDD7

1

1

1

mA

Notes

1 IDD specifications are tested after proper initialization of the device.

2 IDD is dependent on output loading and clock cycle time. Values are specified with minimum cycle time and outputs open.

3 IDD tests have VIL = 0V and VIH = 3V.

4 IDD current will decrease at lower CAS latencies. This is because the lower the latency, the lower the clock cycle time.

5 Address transitions average one transition every two clock cycles.

Notes

4, 5

4,5

4, 5

4,5

4, 5

4,5

4,5

7/5/00

ALLIANCE SEMICONDUCTOR

7

Share Link: