AS4LC8M8S0 查看數據表（PDF） - Alliance Semiconductor
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AS4LC8M8S0 Datasheet PDF : 24 Pages
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AS4LC4M16S0
AS4LC16M4S0
®
AC parameters common to all waveforms
CAS
-75
-8
Sym
Parameter
latency Min Max Min Max
tRRD Row active to row active delay
tRCD RAS to CAS delay time
tRP Row precharge
tRAS Row active
tRC Row cycle time
15 – 20 –
20 – 20 –
20 – 20 –
44 – 50 –
66 – 70 –
tCDL
Last data in to new column
address delay
1– 1 –
tRDL Last data in to row precharge
tBDL Last data in to burst stop
tCCD
Column address to column
address delay
2– 2 –
1– 1 –
1– 1 –
tCK CLK cycle time
3 7.5 – 8 –
2 10 – 10 –
3 5.4 – 6 –
tAC CLK to valid output delay @ 50pF 2
6– 6
–
3 2.7 – 3 –
tOH Output data hold time @ 50 pF
2
3– 3
–
tCH CLK high pulse width
tCL CLK low pulse width
tAS Add setup time
tAH Add hold time
tSLZ CLK to output in low Z
tSHZ CLK to output in high Z
2.5 – 3 –
2.5 – 3 –
1.5 – 2 –
0.8 – 1 –
1– 1 –
3 –6 – 7
2 –6 – 7
tCKH CKE hold time
tCKS CKE setup time
tCMH
CS, RAS, CAS, WE, DQM hold
time
0.8 – 1 –
1.5 – 2 –
0.8 – 1 –
tCMS
CS, RAS, CAS, WE, DQM setup
time
1.5 – 2 –
tDH Data in hold time
tDS Data in setup time
0.8 – 1 –
1.5 – 2 –
-10F
Min Max
20 –
20 –
20 –
50 –
70 –
1
–
2
–
1
–
1
–
10 –
15 –
6
–
6
–
3
–
3
–
3
–
3
–
2
–
1
–
1
–
–
7
–
7
1
–
2
–
1
–
2
–
1
–
2
–
-10
Min Max
20 –
30 –
30 –
60 –
90 –
Unit Notes
ns 1
ns 1
ns 1
ns 1
ns 1
1
– CLK 2
2
– CLK 2
1
– CLK 2
1
– CLK 3
10 –
4
ns
15 –
4
6
–
4,5,7
ns
6
–
4,5,7
3
–
4,5,7
ns
3
–
4,5,7
3
– ns 6
3
– ns 6
2
– ns 6
1
– ns 6
1
– ns 5
–
7
ns
–
7
1
– ns
2
– ns
1
– ns
2
– ns
1
– ns
2
– ns
8
ALLIANCE SEMICONDUCTOR
7/5/00
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