AS4LC8M8S0-10TC 查看數據表（PDF） - Alliance Semiconductor
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AS4LC8M8S0-10TC Datasheet PDF : 24 Pages
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AS4LC8M8S0
AS4LC4M16S0
®
AC parameters common to all waveforms (continued)
CAS
-75
-8
Sym
Parameter
latency Min Max Min Max
tDQD DQM to input data delay
tDQM DQM to data mast during writes
tDQZ
DQM to data high Z during
reads
1– 1 –
0– 0 –
2– 2
–
tDWD
Write command to input data
delay
0– 0
–
tDAL Data-in to active command
tMRD
Load mode register to active/
refresh command
5– 5
–
1– 1
–
tROH
Data-out high Z from
precharge/burst stop command
3
2
3–
2–
3
2
–
–
tCKED
CKE
to CLOCK disable or power-
down entry mode
1– 1
–
tPED
CKE to clock enable or power-
down exit mode
1– 1
–
-10 F
Min Max
1
–
0
–
2
–
0
–
5
–
1
–
3
–
2
–
1
–
1
–
Notes
1 Minimum clock cycles = (Minimum time / clock cycle time) rounded up.
2 Minimum delay required to complete write.
3 Column address change allowed every cycle.
4 Parameters dependent on CAS latency.
5 If clock rising time > 1ns, (tr/2-0.5)ns should be added to parameter.
6 If (tr and tf) > 1ns, [(tr+tf)/2-1]ns should be added to parameter.
7 Outputs measured at 1.5V with 50pF load only without resistive termination.
Burst sequence
Initial address
A1
A0
0
0
0
1
1
0
1
1
Sequential
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
-10
Min Max
1
–
0
–
Unit Notes
CLK
CLK
2
– CLK
0
– CLK
5
– CLK
1
– CLK
3
– CLK 4
2
– CLK 4
1
– CLK
1
– CLK
(BL = 4)
Interleave
1
2
3
0
3
2
3
0
1
2
1
0
Burst sequence
Initial address
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
(BL = 8)
Sequential
Interleave
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7/5/00
ALLIANCE SEMICONDUCTOR
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