AS7C33512PFS18A 查看數據表（PDF） - Alliance Semiconductor

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AS7C33512PFS18A

3.3V 512K × 16/18 pipeline burst synchronous SRAM

Alliance Semiconductor 

Timing waveform of read cycle

CLK

ADSP

ADSC

Address

GWE, BWE

CE0, CE2

tCH

tADSPS

tADSPH

tADSCS

tADSCH

tAS

tAH

A1

A2

tWS

tWH

tCSS

tCSH

®

tCYC

tCL

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A3

AS7C33512PFS16A

AS7C33512PFS18A

CE1

tADVS

tADVH

ADV

OE

DOUT

(pipelined mode) tOE

tLZOE

Q(A1)

tHZOE

tOH

Q(A2)

tCD

ADV INSERTS WAIT STATES

Q(A2Ý01)

Q(A2Ý10) Q(A2Ý11) Q(A3)

tHZC

Q(A3Ý01) Q(A3Ý10)

DOUT

(flow-through mode)

Q(A1)

Q(A2Ý01) Q(A2Ý10)

Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

tHZC

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

BW[a:b] is don’t care.

3/13/01; v.0.9

Alliance Semiconductor

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