AS7C34096-12JI 查看數據表（PDF） - Alliance Semiconductor

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AS7C34096-12JI

5V/3.3V 512K × 8 CMOS SRAM

Alliance Semiconductor 

AS7C4096

AS7C34096

®

Read cycle (over the operating range)3,9

Parameter

Symbo

–10

l Min Max

Read cycle time

tRC 10

–

Address access time

tAA

–

10

Chip enable (CE) access time

tACE

–

10

Output enable (OE) access time tOE –

5

Output hold from address change tOH 3

–

CE Low to output in low Z

tCLZ

3

–

CE High to output in high Z

tCHZ

–

5

OE Low to output in low Z

tOLZ

0

–

OE High to output in high Z

tOHZ –

5

Power up time

tPU

0

–

Power down time

tPD

–

10

–12

Min Max

12

–

–

12

–

12

–

6

3

–

3

–

–

6

0

–

–

6

0

–

–

12

–15

Min Max

15

–

–

15

–

15

–

7

3

–

0

–

–

7

0

–

–

7

0

–

–

15

–20

Min Max

20

–

–

20

–

20

–

8

3

–

0

–

–

9

0

–

–

9

0

–

–

20

Unit Notes

ns

ns 3

ns 3

ns

ns 5

ns 4, 5

ns 4, 5

ns 4, 5

ns 4, 5

ns 4, 5

ns 4, 5

Key to switching waveforms

Rising input

Falling input

Read waveform 1 (address controlled)3,6,7,9

tRC

Address

tAA

DOUT

tOH

Data valid

Undefined/don’t care

Read waveform 2 (CE, OE controlled)3,6,8,9

tRC1

CE

tOE

OE

DOUT

tACE

tOLZ

Data valid

tOHZ

tCHZ

Supply

current

tCLZ

tPU

50%

tPD

ICC

50%

ISB

1/13/05; v.1.9

Alliance Semiconductor

P. 4 of 9

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